1. Field of the Invention
The present invention relates to a DC/DC converter, and more particularly to a DC/DC converter including a circuit for driving the gates in the output stage adaptively as a function of output current.
2. Related Art
DC/DC converter designs today are supporting very high output currents of greater than 100 A. A key challenge at this power level is to reduce power loss to keep system efficiency as high as possible, given other system constraints such as board area, cost, etc. One technique that has been used to improve efficiency in these systems is to adjust the gate drive voltage to minimize the combination of switching loss and conduction loss in the converter.
A known DC/DC power output stage is shown schematically in FIG. 1. As seen, the output stage comprises a pair of power MOSFETs designated CTRL FET and SYNC FET connected in a totem-pole configuration with the source of CTRL FET and the drain of SYNC FET connected together at a node “A”. The drain of CTRL FET is connected to a high voltage supply and the source of SYNC FET is grounded. The CTRL FET is driven with a voltage VGATE and a current IGATE and supplies an output current IOUT at a voltage VOUT. Filter elements LOUT and COUT are also shown.
In this circuit, the switching loss, the gate drive loss, and the conduction loss in CTRL FET are given by the following expressions:
                              Switching  loss                =                              V            GATE                    ·                      I            OUT                    ·                      F            SWX                    ·                                                    Q                GS                            +                              Q                GD                                                    I              GATE                                                          (        1        )                                          Gate  drive  loss                =                              V            GATE                    ·          Qg          ·                      F            SWX                                              (        2        )                                          Conduction  loss                =                              I            OUT            2                    ·                      R            DSON                                              (        3        )            
wherein:
FSWX=switching frequency,
Qg=total charge,
QGS=gate-source charge,
QGD=gate-drain charge, and
RDSON is a function of VGATE.
Conduction losses can be reduced by increasing the gate drive voltage, albeit with diminishing returns.
FIG. 2 is a graph showing total power loss vs. gate drive voltage at 120 A load in a typical converter. As seen, the converter has an optimal gate drive voltage for this current level, where the total power loss reaches a minimum.
However, this known technique of tuning the gate drive voltage to minimize power loss only works well at one load current and is typically set at the maximum output load. In applications where the load current can drop to a very low percentage of full load current, the conduction power loss also decreases rapidly, but the switching power loss still burdens the converter, effectively reducing the overall system efficiency in this lighter load condition. Effectively, the optimal gate drive voltage level which minimizes power loss has changed due to the decreased load current.